CMEOR

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Interpret as CMEOR

MOD_EN_OV_PIT=MOD_EN_OV_PIT_0, MOD_EN_OV_GPT=MOD_EN_OV_GPT_0, MOD_EN_OV_CAN2_CPI=MOD_EN_OV_CAN2_CPI_0, MOD_EN_USDHC=MOD_EN_USDHC_0, MOD_EN_OV_CAN1_CPI=MOD_EN_OV_CAN1_CPI_0, MOD_EN_OV_TRNG=MOD_EN_OV_TRNG_0

Description

CCM Module Enable Overide Register

Fields

MOD_EN_OV_GPT	Overide clock enable signal from GPT - clock will not be gated based on GPT’s signal ‘ipg_enable_clk’ 0 (MOD_EN_OV_GPT_0): don’t override module enable signal 1 (MOD_EN_OV_GPT_1): override module enable signal
MOD_EN_OV_PIT	Overide clock enable signal from PIT - clock will not be gated based on PIT’s signal ‘ipg_enable_clk’ 0 (MOD_EN_OV_PIT_0): don’t override module enable signal 1 (MOD_EN_OV_PIT_1): override module enable signal
MOD_EN_USDHC	overide clock enable signal from USDHC. 0 (MOD_EN_USDHC_0): don’t override module enable signal 1 (MOD_EN_USDHC_1): override module enable signal
MOD_EN_OV_TRNG	Overide clock enable signal from TRNG 0 (MOD_EN_OV_TRNG_0): don’t override module enable signal 1 (MOD_EN_OV_TRNG_1): override module enable signal
MOD_EN_OV_CAN2_CPI	Overide clock enable signal from CAN2 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’ 0 (MOD_EN_OV_CAN2_CPI_0): don’t override module enable signal 1 (MOD_EN_OV_CAN2_CPI_1): override module enable signal
MOD_EN_OV_CAN1_CPI	Overide clock enable signal from CAN1 - clock will not be gated based on CAN’s signal ‘enable_clk_cpi’ 0 (MOD_EN_OV_CAN1_CPI_0): don’t overide module enable signal 1 (MOD_EN_OV_CAN1_CPI_1): overide module enable signal

Links

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